 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ? semiconductor components industries, llc, 2013 may, 2013 ? rev. 1 1 publication order number: NCP1850/d NCP1850 fully integrated li-ion switching battery charger with power path management and usb on-the-go support the NCP1850 is a fully programmable single cell lithium ? ion switching battery charger optimized for charging from a usb compliant input supply and ac adaptor power source. the device integrates a synchronous pwm controller, power mosfets, and the entire charge cycle monitoring including safety features under software supervision. an optional battery fet can be placed between the system and the battery in order to isolate and supply the system. the NCP1850 junction temperature and battery temperature are monitored during charge cycle, and both current and voltage can be modified accordingly through i 2 c setting. the charger activity and status are reported through a dedicated pin to the system. the input pin is protected against overvoltages. the NCP1850 also provides usb otg support by boosting the battery voltage as well as providing overvoltage protected power supply for usb transceiver. features ? 1.5 a buck converter with integrated pass devices ? input current limiting to comply to usb standard ? automatic charge current for ac adaptor charging ? high accuracy voltage and current regulation ? input overvoltage protection up to +28 v ? factory mode ? 250 ma boosted supply for usb otg peripherals ? reverse leakage protection prevents battery discharge ? protected usb transceiver supply switch ? dynamic power path with optional battery fet ? battery temperature sensing for safe operation ? silicon temperature supervision for optimized charge cycle ? safety timers ? flag output for charge status and interrupts ? intb output for interrupts ? i 2 c control bus up to 3.4 mhz ? small footprint 2.2 x 2.55 mm csp package ? these devices are pb ? free and are rohs compliant applications ? smart phone ? handheld devices ? tablets ? pdas marking diagram http://onsemi.com see detailed ordering and shipping information in the package dimensions sect ion on page 29 of this data sheet. ordering information 1850 ayww 1850 = specific device code a = assembly location y = year ww = work week = pb ? free package wlcsp25 case 567fz
NCP1850 http://onsemi.com 2 pin connections figure 1. package outline csp (top view) cboot e trans core weak bat pgnd pgnd sensp sensn fet d sw sw agnd ilim ntc c cap cap otg ilimb flag b in in spm sda scl a 12345 table 1. pin function description pin name type description a1 in power battery charger input. these two pins must be decoupled by at least 1 f capacitor and connected together. a2 in power a3 spm digital input system power monitor input. a4 sda digital bidirectional i 2 c data line a5 scl digital input i 2 c clock line b1 cap power cap pin is the intermediate power supply input for all internal circuitry. bypass with at least 4.7 f capacitor. must be tied together. b2 cap power b3 otg digital input enables otg boost mode. otg = 0, the boost is powered off otg = 1 turns boost converter on b4 ilimb open drain output connect to interrupt pin of the system, active low b5 flag open drain output charging state active low. this is an open drain pin that can either drive a status led or connect to interrupt pin of the system. c1 sw analog output connection from power mosfet to the inductor. these pins must be connected together. c2 sw analog output c3 agnd analog ground analog ground / reference. this pin should be connected to the ground plane and must be connected together. c4 ilim digital input input current limiter level selection (can be defeated by i 2 c). c5 ntc analog input input for the battery ntc (10 k / b = 3900) or (4.7 k / b = 3900) if not used, this pin must be tied to gnd to configure the NCP1850 and warn that ntc is not used. d1 pgnd power gnd power ground. these pins should be connected to the ground plane and must be connected together. d2 pgnd power gnd d3 sensp analog input current sense input. this pin is the positive current sense input. it should be connected to the r sense resistor positive terminal. NCP1850 http://onsemi.com 3 table 1. pin function description pin description type name d4 sensn analog input current sense input. this pin is the negative current sense input. it should be connected to the r sense resistor negative terminal. this pin is also voltage sense input of the voltage regulation loop when the fet is present and open. d5 fet analog output battery fet driver output. when not used, this pin must be directly tied to ground. e1 cboot analog in/out floating bootstrap connection. a 10 nf capacitor must be connected between cboot and sw. e2 trans analog output output supply to usb transceiver. this pin can source a maximum of 30 ma to the external usb phy or any other ic that needs +5 v usb. this pin is overvoltage protected and will never be higher than 5.5 v. this pin should be bypassed by a 100 nf ceramic capacitor. e3 core analog output 5 v reference voltage of the ic. this pin should be bypassed by a 2.2 f capacitor. no load must be connected to this pin. e4 weak analog output weak battery charging current source input. e5 bat analog input battery connection NCP1850 http://onsemi.com 4 table 2. maximum ratings rating symbol value unit in (note 1) v in ? 0.3 to +28 v cap (note 1) v cap ? 0.3 to +28 v power balls: sw, cboot (note 1) v pwr ? 0.3 to +24 v in pin with respect to vcap v in_cap ? 0.3 to +7.0 v sw with respect to sw v sw_cap ? 0.3 to +7.0 v sense/control balls: sensp, sensn, vbat, fet, trans, core, ntc, flag, intb and weak. (note 1) v ctrl ? 0.3 to +7.0 v digital input: scl, sda, spm, otg, ilim (note 1) input voltage input current v dg i dg ? 0.3 to +7.0 v 20 v ma human body model (hbm) esd rating are (note 2) esd hbm 2000 v machine model (mm) esd rating are (note 2) esd mm 200 v latch up current (note 3): all digital pins( v dg ), fet all others pins. i lu 10 100 ma storage temperature range t stg ? 65 to + 150 c maximum junction temperature (note 4) t j ? 40 to + tsd c moisture sensitivity (note 5) msl level 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. with respect to pgnd. according to jedec standard jesd22 ? a108 2. this device series contains esd protection and passes the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22 ? a114 for all pins. machine model (mm) 200 v per jedec standard: jesd22 ? a115 for all pins. 3. latch up current maximum rating: 100 ma or per 10 ma jedec standard: jesd78 class ii. 4. a thermal shutdown protection avoids irreversible damage on the device due to power dissipation. see electrical characteristi cs. 5. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020. table 3. operating conditions symbol parameter conditions min typ max unit v in operational power supply (note 6) 3 v inov v v dg digital input voltage level 0 5.5 v t a ambient temperature range ? 40 25 +85 c i sink flag sink current 10 ma c in decoupling input capacitor 1 f c cap decoupling switcher capacitor 4.7 f c core decoupling core supply capacitor 2.2 f c out decoupling system capacitor 10 f l x switcher inductor 2.2 h r sns current sense resistor 68 m r ja thermal resistance junction ? to ? air (notes 7 and 8) 60 c/w t j junction temperature range ? 40 25 +125 c 6. ovlo is selectable per metal option (see electrical characteristics table). 7. a thermal shutdown protection avoids irreversible damage on the device due to power dissipation. see electrical characteristi cs. 8. the r ja is dependent on the pcb heat dissipation. board used to drive this data was a 2s2p jedec pcb standard. NCP1850 http://onsemi.com 5 table 4. electrical characteristics min & max limits apply for t a between ? 40 c to +85 c and t j up to + 125 c for v in between 3.6 v to 7 v (unless otherwise noted). typical values are referenced to t a = + 25 c and v in = 5 v (unless otherwise noted). symbol parameter conditions min typ max unit input voltage v indet valid input detection threshold v in rising 3.55 3.6 3.65 v v in falling 2.95 3.0 3.05 v v busuv usb under voltage detection v in falling 4.3 4.4 4.5 v hysteresis 50 100 150 mv v busov usb over voltage detection v in rising 5.55 5.65 5.75 v hysteresis 25 75 125 mv v inov v inov valid input high threshold v in rising 7.1 7.2 7.3 v hysteresis 200 300 400 mv input current limiting i inlim input current limit v in = 5 v i inlim set to 100 ma 70 85 100 ma i inlim set to 500 ma 425 460 500 ma i inlim set to 900 ma 800 850 900 ma i inlim set to 1500 ma 1.4 1.45 1.5 a input supply current i q_sw vbus supply current no load, charger active state 15 ma i off charger not active, ntc disable 500 a charger detection v chgdet charger detection threshold voltage v in ? v sensn , v in rising 50 200 mv v in ? v sensn , v in falling 10 50 reverve blocking current i leak v bat leakage current battery leakage, v bat = 4.2 v v in = 0 v, sda = scl = 0 v 5 7 a r rbfet input rbfet on resistance (q1) charger active state, measured between in and cap,v in = 5 v ? 45 90 m battery and system voltage regulation v chg output voltage range programmable by i 2 c 3.3 4.5 v default value 3.6 voltage regulation accuracy constant voltage mode, t a = 25 c ? 0.5 0.5 % ? 1 1 i2c programmable granularity 25 mv battery voltage threshold v safe safe charge threshold voltage v bat rising 2.1 2.15 2.2 v v pre conditioning charge threshold voltage vfet = 3.1 v and 3.2 v 2.95 3 3.05 v vfet = 3.3 v, 3.4 v, 3.5 v and 3.6 v 3.15 3.2 3.25 9. minimum transition time from states to states. NCP1850 http://onsemi.com 6 table 4. electrical characteristics min & max limits apply for t a between ? 40 c to +85 c and t j up to + 125 c for v in between 3.6 v to 7 v (unless otherwise noted). typical values are referenced to t a = + 25 c and v in = 5 v (unless otherwise noted). symbol unit max typ min conditions parameter battery voltage threshold v fet end of weak charge threshold voltage v bat rising voltage range 3.15 3.2 3.25 v default value 3.4 accuracy ? 2 2 % i 2 c programmable granularity 100 mv v rechg recharge threshold voltage relative to v chg setting register 97 % v buckov overvoltage threshold voltage v bat rising, relative to v chg setting register, measured on sensn or sensp, q bat close or no q bat 115 % q bat open. 5 v charge current regulation i chg charge current range programmable by i 2 c 400 1600 ma default value 950 1000 1050 ma charge current accuracy ? 50 50 ma i 2 c programmable granularity 100 ma i pre pre ? charge current v bat < v pre 405 450 495 ma i safe safe charge current v bat < v safe 8 10 12 ma i weak weak battery charge current batfet present, v safe < v bat < v fet 80 100 120 ma charge termination i eoc charge current termination v bat v rechg current range 100 275 ma default value 150 accuracy, i eoc < 200 ma ? 25 25 i 2 c programmable granularity 25 flag v fol flag output low voltage i flag = 10 ma 0.5 v i fleak off ? state leakage v flag = 5 v 1 a digital input (v dg ) v ih high ? level input voltage 1.2 v v il low ? level input voltage 0.4 v r dg pull down resistor 500 k i dleakk input current v dg = 0 v ? 0.5 0.5 a i 2 c v sysuv cap pin supply voltage i 2 c registers available 2.5 v v i 2 cint * high level at scl/sca line 1.7 5 v v i 2 cil scl, sda low input voltage 0.4 v v i 2 cih scl, sda high input voltage 0.8 * v i 2 cint v 9. minimum transition time from states to states. NCP1850 http://onsemi.com 7 table 4. electrical characteristics min & max limits apply for t a between ? 40 c to +85 c and t j up to + 125 c for v in between 3.6 v to 7 v (unless otherwise noted). typical values are referenced to t a = + 25 c and v in = 5 v (unless otherwise noted). symbol unit max typ min conditions parameter i 2 c v i 2 col scl, sda low output voltage i sink = 3 ma 0.3 v f scl i 2 c clock frequency 3400 khz junction thermal management t sd thermal shutdown rising 125 140 150 c falling 115 c t h2 hot temp threshold 2 relative to t sd ? 7 c t h1 hot temp threshold 1 relative to t sd ? 11 c t warn thermal warning relative to t sd ? 15 c battery thermal management v ntcrmv battery removed threshold voltage v ntc rising 2.3 2.325 2.4 v v cold battery cold temperature cor- responding voltage threshold batcold[1:0]: 00 1.775 1.8 1.825 batcold[1:0]:01 1.7 1.725 1.75 batcold[1:0]:10 1.625 1.65 1.675 batcold[1:0]:11 1.55 1.575 1.6 v hot battery hot temperature cor- responding voltage threshold bathot[1:0]: 00 800 825 850 mv bathot[1:0]:01 725 750 775 bathot[1:0]:10 650 675 700 bathot[1:0]:11 575 600 625 v ntcdis ntc disable corresponding voltage threshold v ntc falling 50 75 100 mv v reg internal voltage reference 2.35 2.4 2.45 v r ntcpu internal resistor pull up 9.8 10 10.2 k buck converter f swchg switching frequency ? 3 ? mhz switching frequency accuracy ? 10 +10 % t dtyc max duty cycle average 99.5 % i pkmax maximum peak inductor current 1.9 a r onls low side buck mosfet r dson (q3) measured between pgnd and sw, v in = 5 v ? 170 350 m r onhs high side buck mosfet r dson (q2) measured between cap and sw, v in = 5 v ? 140 285 m protected transceiver supply v trans voltage on trans pin v in 5 v 5 5.5 v i trmax trans current capability 30 ma timing t wd watchdog timer 32 s t usb usb timer 2048 s 9. minimum transition time from states to states. NCP1850 http://onsemi.com 8 table 4. electrical characteristics min & max limits apply for t a between ? 40 c to +85 c and t j up to + 125 c for v in between 3.6 v to 7 v (unless otherwise noted). typical values are referenced to t a = + 25 c and v in = 5 v (unless otherwise noted). symbol unit max typ min conditions parameter timing t chg1 charge timer safe ? charge or pre ? charge or weak ? safe or weak ? charge state. 3 h t chg2 full ? charge state 2 h t wu wake ? up timer 64 s t vrchr deglitch time for end of charge voltage detection v bat rising 15 ms v bat falling 127 ms t indet deglitch time for input voltage detection v in rising 15 ms t dgs1 deglitch time for signal crossing i eoc , v pre , v safe , v chgdet , v inext thresholds. rising and falling edge 15 ms t dgs2 deglitch time for signal crossing v fet , v busuv , v busov thresholds. rising and falling edge 1 ms t stwc charger state timer (note 9) from weak charge to full charge state 32 s t stw from wait to charger active state 128 ms t st from weak charge to full charge state, triggered on tst_set level transition. tst_set = 0 32 24 s tst_set = 1 16 ms all others states 16 ms boost converter and otg mode v ibstl boost minimum input operating range boost start ? up 3.1 3.2 3.3 v boost running 2.9 3 3.1 v ibsth boost maximum input operating range 4.4 4.5 4.6 v v obst boost output voltage dc value measured on cap pin, no load 5.00 5.1 5.15 v v obstac boost output voltage accuracy measured on cap pin including line and load regulation ? 3 3 % i bstmx output current capability 250 ma f swbst switching frequency 1.5 mhz switching frequency accuracy ? 10 10 % i bpkm maximum peak inductor current 1.9 a v obstol boost overload boost running , voltage on in pin 4.3 4.4 4.5 v t obstol maximum capacitance on in pin during start ? up 10 f r obstol maximum load on in pin during start ? up 50 v obstov overvoltage protection v in rising 5.55 5.65 5.75 v hysteresis 25 75 125 mv 9. minimum transition time from states to states. NCP1850 http://onsemi.com 9 block diagram figure 2. block diagram cboot sw in cap pgnd core ntc bat fet weak sensn sensp trans scl sda ilim otg spm agnd flag intb c boot 10nf c in c cap c core 4.7 f 2.2 f 1 f usb phy c trs 0.1 f + c sys r sns l x 2.2 f 68m 10 f vbus d+ d ? gnd q bat* * optional charge pump 5v reference v busuv v busov v indet v inov v safe v pre v fet v rechg v batov v chgdet v cold v hot v rmoved v bat current, voltage, and clock reference v reg v bat v in v reg pwm generator i2c & digital controler v tj t sd t h2 t h1 t warn i inreg v core r ntcpu v ntcdis v tj + ? + ? + ? + ? + ? + ? + ? + ? + ? + + ? + ? + ? + ? + ? + ? + ? q1 q2 q3 amp drv + ? drv v chg batfet detection & drive drv v cap + ? i chg i eoc i bat + ? + ? v core v core v cap i chg drv drv NCP1850 http://onsemi.com 10 typical application circuits figure 3. usb charger with battery external mosfet figure 4. usb charger without battery external mosfet in flag scl sda spm cap ntc bat fet weak sensn sensp cboot sw ilim agnd pgnd otg + NCP1850 core system vbus d+ d ? id gnd c in c cap c core c boot c out r sns l x 4.7 f 2.2 f 1 f 10nf 2.2 h 68m 10 f q bat (*) intb trans c trans 100nf ntc bat fet weak sensn sensp cboot sw + NCP1850 system 10nf 2.2 f 10 f c boot c sys r sns l x 68m in cap agnd pgnd core c in c cap c core 4.7 f 2.2 f 1 f flag scl sda spm otg ilim intb trans c trans 100nf vbus d+ d ? id gnd NCP1850 http://onsemi.com 11 charge mode operation overview the NCP1850 is a fully programmable single cell lithium ? ion switching battery charger optimized for charging from a usb compliant input supply. the device integrates a synchronous pwm controller; power mosfets, and monitoring the entire charge cycle including safety features under software supervision. an optional battery fet can be placed between the system and the battery in order to isolate and supply the system in case of weak battery. the NCP1850 junction temperature and battery temperature are monitored during charge cycle and current and voltage can be modified accordingly through i 2 c setting. the charger activity and status are reported through a dedicated pin to the system. the input pin is protected against overvoltages. the NCP1850 is fully programmable through i 2 c interface (see registers map section for more details). all registers can be programmed by the system controller at any time during the charge process. the charge current (i chg ), charge voltage (v chg ), and input current (i inlim ) are controlled by a dynamic voltage and current scaling for disturbance reduction. is typically 10 s for each step. NCP1850 also provides usb otg support by boosting the battery voltage as well as an over voltage protected power supply for usb transceiver. charge profile in case of application without q fet (see figure 4), the NCP1850 provides four main charging phases as described below. unexpected behavior or limitations that can modify the charge sequence are described further (see charging process section). figure 5. typical charging profile of NCP1850 v safe v pre v rechg v chg i chg i pre i eoc i safe safe charge pre charge constant current constant voltage end of charge v bat i bat safe charge: with a disconnected battery or completely empty battery, the charge process is in safe charge state, the char ge current is set to i safe in order to charge up the system?s capacitors or the battery. when the battery voltage reaches v safe threshold, the battery enters in pre ? conditioning. pre conditioning (pre ? charge): in preconditioning (pre charge state), the dc ? dc convertor is enabled and an i pre current is delivered to the battery. this current is much lower than the full charge current. the battery stays in preconditioning until the v bat voltage is lower than v pre threshold. constant current (full charge): in the constant current phase ( full charge state), the dc ? dc convertor is enabled and an i chg current is delivered to the load. as battery voltage could be suf ficient, the system may be awake and sink an amount of current. in this case the charger output load is composed of the battery and the system. thus i chg current delivered by the NCP1850 is shared between the battery and the system: i chg = i sys + i bat . NCP1850 http://onsemi.com 12 system awake figure 6. typical charging profile of NCP1850 with system awake v safe v pre v rechg v bat v chg v bat i bat i sys i bat i safe i eoc i pre i chg safe charge pre charge constant current constant voltage end of charge i chg current is programmable using i 2 c interface (register ibat_set ? bits ichg[3:0]). constant v oltage (full charge): the constant voltage phase is also a part of the full charge state. when the battery voltage is close to its maximum (v chg ), the charge circuit will transition from a constant current to a constant voltage mode where the charge current will slowly decrease (taper off). the battery is now voltage controlled. v chg voltage is programmable using i 2 c interface (register vbat_set ? bits ctrl_vbat[5:0]). end of c harge: the charge is completed ( end of charge state) when the battery is above the v rechg threshold and the charge current below the i eoc level. the battery is considered fully charged and the battery charge is halted. charging is resumed in the constant current phase when the battery voltage drops below the v rechg threshold. i eoc current is programmable using i 2 c interface (register ibat_set ? bits ieoc[2:0]). the charge cycle can also be halted manually through i 2 c (register crtl2 bit chg_halt=1). power stage control NCP1850 provides a fully ? integrated 3 mhz step ? down dc ? dc converter for high efficiency. for an optimized charge control, three feedback signals controls the pwm duty cycle. these three loops are: maximum input current (i inlim ), maximum charge current (i chg ) and, maximum charge voltage (v chg ). the switcher is regulated by the first loop that reaches its corresponding threshold . typically during charge current phase (v pre < v bat < v rechg ), the measured input current and output voltage are below the programmed limit and asking for more power. but in the same time , the measured output current is at the programmed limit and thus regulates the dc ? dc converter . in order to prevent battery discharge and overvoltage protection, q1(reverse voltage protection) and q2 (high side n ? mosfet of the dc ? dc converter) are mounted in a back ? to ? back common drain structure while q3 is the low side n mosfet of the dc ? dc converter. q2 gate driver circuitry required an external bootstrap capacitor connected between cboot pin and sw pin. an internal current sense monitors and limits the maximum allowable current in the inductor to i peak value. charger detection, start ? up sequence and system off the start ? up sequence begins upon an adaptor valid voltage plug in detection: v in > v indet and v in ? v bat > v chgdet ( off state). then, the internal circuitry is powered up and the presence of ntc and batfet are reported (register status ? bit batfet and ntc). when the power ? up sequence is done, the charge cycle is automatically launched. at any time and any state, the user can holds the charge process and transit to fault state by setting chg_en to ?0? (register ctrl1) in the i 2 c register. furthermore, during fault state, ntc block can be disabled for power saving (bit ntc_en register ctrl1) the i2c registers are accessible without valid voltage on v in if v cap > v sysuv (i.e. if v bat is higher than v sysuv + voltage drop across q2 body diode) . at any time, the user can reset all register stack (register ctrl1 ? bit reg_rst). NCP1850 http://onsemi.com 13 weak battery support an optional battery fet (q bat ) can be placed between the application and the battery. in this way, the battery can be isolated from the application and so ? called weak battery operation is supported. typically, when the battery is fully discharged, also referred to as weak battery, its voltage is not sufficient to supply the application. when applying a charger, the battery first has to be pre ? charged to a certain level before operation. during this time; the application is supplied by the dc ? dc converter while integrated current sources will pre ? charge the battery to the sufficient level before reconnecting. the pin fet can drive a pmos switch (q bat ) connected between bat and weak pin. it is controlled by the charger state machine (charging process section). the basic behavior of the fet pin is that it is always low. thus the pmos is conducting, except when the battery is too much discharged at the time a charger is inserted under the condition where the application is not powered on. the fet pin is always low for bat above the v fet threshold. some exceptions exist which are described in the charging process and power path management section. the v fet threshold is programmable (register misc_set ? bit ctrl_vfet). batfet d etection the presence of a pmos (q bat ) at the fet pin is verified by the charging process during its config state. to distinguish the two types of applications, in case of no battery fet the pin fet is to be tied to ground. in the config state an attempt will be made to raise the fet pin voltage slightly up to a detection threshold. if this is successful it is considered that a battery fet is present. the batfet detection is completed for the whole charge cycle and will be done again upon unplug condition (v bat < v indet or v in ? v bat < v chgdet ) or register reset (register ctrl1? bit reg_rst). weak w ait weak wait state is entered from wait state (see charging process section) in case of ba tfet present, battery voltage lower than v fet and host system in shutdown mode (spm = 0). the dcdc converter from vin to sw is enabled and set to v chg while the battery fet q bat is opened. the system is now powered by the dc ? dc. the internal current source to the battery is disabled. in weak wait state, the state machine verifies if the battery temperature is ok thanks to the ntc sensor. if ntc ok or if ntc is not present (ntc pin tied to 0), this state is left for weak safe state. in case of no battery, the NCP1850 stay in weak wait state (the system is powered by dc ? dc). weak s afe the voltage at v bat , is below the v safe threshold. in weak safe state, the battery is charged with a linear current source at a current of i safe . the dc ? dc converter is enabled and set to v chg while the battery fet q bat is opened. in case the ilim pin is not made high or the input current limit defeated by i 2 c before timer expiration, the state is left for the safe charge state after a certain amount of time (see wake up timer section). otherwise, the state machine will transition to the weak charge state once the battery is above v safe . weak c harge the voltage at v bat , is above the v safe threshold. the dc ? dc converter is enabled and set to v chg . the battery is initially charged at a charge current of i weak supplied by a linear current source from weak pin (i.e. dc ? dc converter) to bat pin. i weak value is programmable (register misc_set bits iweak). the weak charge timer (see w ake up t imer section) is no longer running. when the battery is above the v fet threshold (programmable), the state machine transitions to the full charge state thus batfet q bat is closed. NCP1850 http://onsemi.com 14 v safe v fet v chg i bat v bat weak charge constant current constant voltage end of charge weak safe weak wait v rechg i sys v bat i bat v sys i out i chg i weak i safe i eoc figure 7. weak charge profile in some application cases, the system may not be able to start in weak charge states due to current capability limitation or/and configuration of the system. if so, in order to avoid unexpected ?drop and retry? sequence of the buck output, the charge state machine allows only three system power ? up sequences based on spm pin level: if spm pin level is toggled three times during weak charge states, the system goes directly to safe charge state and a full charge mode sequence is initiated (?power fail? condition in charging process section). power path management power path management can be supported when a battery fet (q bat ) is placed between the application and the battery. when the battery is fully charged (end of charge state), power path management disconnects the battery from the system by opening q bat , while the dc ? dc remains active. this will keep the battery in a fully charged state with the system being supplied from the dc ? dc. if a load transient appears exceeding the dc ? dc output current and thus causing v sensen to fall below v rechg , the fet q bat is instantaneously (within t ppm , see electrical characteristics ) closed to reconnect the battery in order to provide enough current to the application. the fet q bat remains closed until the end of charge state conditions are reached again or manually set through i 2 c (register crtl2 bit chg_halt = 1) . the power path management function is enabled through the i 2 c interface (register crtl2 bit pwr_path = 1). safety timer description the safety timer ensures proper and safe operation during charge process. the set and reset condition of the different safety timer (watchdog timer, charge timer, wakeup timer and usb timer) are detailed below. when a timer expires (condition ?timeout? in charging process section), the charge process is halted. watchdog timer watchdog timer ensures software remains alive once it has programmed the ic. the watchdog timer is no longer running since i 2 c interface is not available. upon an i 2 c write, automatically a watchdog timer t wd is started. the watchdog timer is running during charger active states and fault state. another i 2 c write will reset the watchdog timer. when the watchdog times out, the state machine reverts to fault state and reported through i 2 c interface (register chint2? bit wdto). also used to time out the fault state. this timer can be disabled (register ctrl2 bit wdto_dis). charge timer a charge timer t chg is running that will make that the overall charge to the battery will not exceed a certain amount of energy. the charge timer is running during charger active states and halted during charger not active states (see charging process section). the timer can also be cleared any time through i 2 c (register ctrl1 ? bit tchg_rst). the state machine transitions to fault state when the timer expires. this timer can be disabled (register ctrl2 bit chgto_dis). usb timer a usb charge timer t usb is running in the charger active states while halted in the char ger non active states. the timer keeps running as long as the lowest input current limit NCP1850 http://onsemi.com 15 remains selected either by ilim pin or i 2 c (register i_set ? bit iinlim and iinlim_en). this will avoid exceeding the maximum allowed usb charge time for un ? configured connections. when expiring, the state machine will transition to fault state. the timer is cleared in the off state or by i 2 c command (register ctrl1 ? bit tchg_rst). wake up timer before entering weak charge state, NCP1850 verifies if the input current available is enough to supply both the application and the charge of the battery. a wake ? up timer t wu verifies if ilim pin is raised fast enough or application powered up (by monitoring register i_set ? bit iinlim and iinlim_en level) after a usb attachment. the wake up timer is running in weak wait state and weak safe state and clears when the input current limit is higher than 100 ma. input current limitation in order to be usb specification compliant, the input current at v in is monitored and could be limited to the i inlim threshold. the input current limit threshold is selectable through the ilimx pin. when low, the one unit usb current is selected (i in 100 ma), where when made high 5 units are selected (i in 500 ma). in addition, this current limit can be programmed through i 2 c (register misc_set bits iinlim) therefore defeating the state of the ilimx pin. in case of non ? limited input source, current limit can be disabled (register ctrl2 bit iinlim_en). the current limit is also disabled in case the input voltage exceeds the v busov threshold. end of charge constant voltage v safe v pre v rechg v chg v bat constant current safe charge pre charge i bat i safe i eoc i pre i chg figure 8. typical charging profile of NCP1850 with input current limit input voltage based automatic charge current if the input power source capability is unknown, automatic charge current will automatically increase the charge current step by step until the v in drops to v busuv . upon v busuv being triggered, the charge current i chg is immediately reduced by 1 step and stays constant until v in drops again to v busuv . the ichg current is clamped to the i 2 c register value (register ibat_set, bits ichg). this unique feature is enabled through i 2 c register (register crtl2 bit aicl_en). junction temperature management during the charge process, NCP1850 monitors the temperature of the chip. if this temperature increases to t wa rn , an interrupt request (described in section charge status reporting) is generated and bit twarn_sns is set to ?1? (register ntc_th_sense). knowing this, the user is free to halt the charge (register ctrl ? bit chg_en) or reduce the charge current (register i_set ? bits ichg). when chip temperature reaches t sd value, the charge process is automatically halt. between t wa rn and t sd threshold, a junction temperature management option is available by setting 1 to tj_warn_opt bit (register control). in this case, if the die temperature hits t m1 threshold, an interrupt is generated again but NCP1850 will also reduce the charge current i chg by two steps or 200 ma. this should in most cases stabilize the die temperature because the power dissipation will be reduced by approximately 50 mw. if the die temperature increases further to hit t m2 , an interrupt is generated and the charge current is reduced to its lowest NCP1850 http://onsemi.com 16 level or 400ma. the initial charge current will be re ? established when the die temperature falls below the t wa rn again. if bit tj_warn_opt = 0 (register ctrl1), the charge current is not automatically reduced, no current changes actions are taken by the chip until t sd . battery temperature management for battery safety, charging is not allowed for too cold or too hot batteries. the battery temperature is monitored through a negative temperature coefficient (ntc) thermistor mounted in the battery pack or on the phone pcb close to the battery pack. in some cases the ntc is handled by the platform and will not be connected to the charger ic. NCP1850 provides a ntc pin for monitoring an external ntc thermistor. ntc pin is connected to an internal voltage v reg through pull ? up resistor (r ntcpu ). by connecting a ntc thermistor between ntc pin and gnd, internal comparators can monitors voltage variation and provides temperature information to the state machine. + ? + ? + ? + ntc + ? + ? NCP1850 + ? figure 9. ntc monitoring circuit r ntcpu v reg v rmoved v cold v chilly v warm v hot v ntcdis two thresholds ?cold? and ?hot? are provided those are programmable. the corresponding voltage levels of these thresholds are respectively v cold and v hot . interrupts (describe in section charge status reporting) are generated when crossing either threshold. the charge is halted outside the cold ? hot window. in addition to the above, comparators monitor the ntc presence. when the ntc is removed (v ntc > v ntcrmv ) , no more charge current is supplied to the battery and an interrupt is generated (describe in section charge status reporting). this functionality can be disabled through programming (bit ntc_en in register ctrl1). when the ntc is not used in the application the ntc pin can be tied to ground (v ntc < v ntcdis ) which will disable the battery temperature monitoring function. regulated power supply (trans pin) NCP1850 has embedded a linear voltage regulator (v trans ) able to supply up to i trmax to external loads. this output can be used to power usb transceiver. trans pin is enabled if a v bus valid is connected on input pin (v busuv < v in < v busov ) and can be disabled through i 2 c (bit trans_en_reg register ctrl2). a current limiter protects the ic in case of short circuit on trans pin. charge status reporting charge s tatus on flag p in flag pin is used to report charge status to the system processor and also for interruption request. during charger active states and wait state, the pin flag is low in order to indicate that the charge of the battery is in progress. when charge is completed or disabled or a fault occurs, the flag pin is high as the charge is halted. interruption on flag pin upon any state or status change, the system controller can be informed by sensing flag pin. a t flagon pulse is generated on this pin in order to signalize all events listed in the stat_int, ch1_int, ch2_int, bst_int registers. all these bits are read to clear. the register map indicated the active transition of each bits (column ?type? register map section). if more than 1 interrupt appears, only 1 pulse is generated while interrupt registers (st at_int, ch1_int, ch2_int, bst_int) will not fully clear. the level of this pulse depends on the state of the charger (see charging process section): ? when charger in is charger active states and wait state the flag is low and consequently the pulse level on flag pin is high. ? in the others states, the pulse level is low as the flag stable level is high. this pulse can be globally masked due to the int_flg_mask bit (register ctrl1). interruption on intb p in upon any state or status change, the system controller can be informed by sensing intb pin. this pin is tied low in order to signalize all events listed in the stat_int, ch1_int, ch2_int, bst_int registers and can be individually masked with the corresponding mask bits in registers stat_msk, ch1_msk, ch2_msk and bst_msk. all interrupt signals on intb pin can be masked with the global interrupt mask bit (bit int_mask register ctrl1). all these bits are read to clear. the register indicated the active transition of each bits (column ?type? register map section). NCP1850 http://onsemi.com 17 if more than 1 interrupt appears, the intb pin stay low while interrupt registers (sta t_int, ch1_int, ch2_int, bst_int) will not fully clear. status and control r egisters the status register contains the current charge state, ntc and batfet connection as well as fault and status interrupt (bits int_reg in register status). the charge state (bits state in register status) is updated on the fly and corresponds to the charging state describe in charging process section. an interruption (see description below) is generated upon a state change. in the config state, hardware detection is performed on baftet and ntc pins. from wait state, their statuses are available (bit batfet and ntc in register status). int_reg bits are different to 0 if an interruption appears (see description below). thanks to this register, the system controller knows the chip status with only one i 2 c read operation. if a fault appears or a states change the controller can read corresponding registers for more details. sense and s tatus r egisters at any time the system processor can know the status of all the comparators inside the chip by reading vin_sns, vbat_sns, and temp_sns registers (read only). these bits give to the system controller the real time values of all the corresponding comparators outputs (see block diagram ). battery removal and no battery operation during normal charge operation the battery may bounce or be removed. the state transition of the state machine only occurs upon deglitched signals which allow bridging any battery bounce. true battery removal will last longer than the debounce times. the NCP1850 responses depend on ntc and batfet presence: if the battery is equipped with an ntc its removal is detected (v ntc > v ntcrmv ) and the state machine transits to fault state and an interrupt is generated (bit batrmv register ch1_int). then, in case of applications with batfet, the state machine will end up in weak wait state so the system is powered by the dc ? dc converter (see weak wait section) without battery. in case of application without batfet, the state machine will end up in fault state (dc ? dc off) so the system is not powered. with a battery pack without ntc support, the voltage at v bat will rapidly reach the dcdc converter setting v chg and then transition to end of charge state causing dc ? dc off. thus v bat falls (?battery fail? condition in charging process section). factory mode during factory testing no battery is present in the application and a supply could be applied through the bottom connector to power the application. the state machine will support this mode of operation under the condition that the application includes a battery fet and uses batteries with ntc support (similar as no battery operation). in this case, the state machine will end up in weak wait state (see weak wait section). the application is supplied while the absence of the battery pack is interpreted as a battery pack out of temperature (v ntc > v cold ). through i 2 c the device is entirely programmable so the controller can configure appropriate current and voltage threshold for handle factory testing. factory regulation mode (register misc_set bit fctry_mod_reg) is accessible for factory testing purpose. in this mode, input and charge current loops are disabled, allowing full power to the system. NCP1850 http://onsemi.com 18 charging process figure 10. detailed charging process * see power path management section. v bat >v safe and i inlim 500ma v bat > v pre v bat >v fet v bat > v safe v bat < v safe ? v bat >v rechg and ? ( bat v inov or ? v bat >v buckov or ? timeout or - power fail or ? t j >t sd or ? chr_en = 0 fault removed and chr_en = 1 ? timeout ? t j >t sd or ? v in > v inov or ? v bat >v buckov or ? v ntc > v ntcrmv or ? chr_en = 0 start charging : v cold > v ntc > v warm ? timeout ? t j >t sd or ? v in > v inov or ? v bat >v batov or ? chr_en = 0 v bat < v pre start charging : v ntc < v cold or v ntc > v warm halt charging : v ntc > v cold or v ntc < v warm or battery fail v ntc > v cold or v ntc < v warm or v bat > v safe halt charging : v ntc > v cold or v ntc < v warm charger active: weak charge mode charger active: full charge mode ? buck: off ? iweak : off ? isafe: off ? flag : high ? qfet: on ? charger off iq < ioff ? i c available ? t j >t sd or ? v in > v inov or ? v ntc > v ntcrmv or ? chr_en = 0 v cap > v sysuv ? v in > v indet and ? v in ? v bat > v chgdet power ? up and detection done charger not active mode ? v in < v indet or ? v in ? v bat < v chgdet reg_rst = 1 fault weak wait weak safe weak charge full charge pre charge safe charge off end of charge ? power ? up ? ntc and batfet detection ? q1: on config wait ? buck: off ? iweak : off ? isafe: off ? flag : low ? qfet: on any state ? buck: off* ? iweak : off ? isafe: off ? flag : high ? qfet: on* ? buck: off ? iweak : off ? isafe: on ? flag : low ? qfet: on ? buck: on (precharge) ? iweak :off ? isafe: off ? flag : low ? qfet: on ? buck: on ? iweak :off ? isafe: off ? flag : low ? qfet: on ? buck: on ? iweak : on ? isafe: off ? flag : low ? qfet: off ? buck: on ? iweak : off ? isafe: on ? flag : low ? qfet: off ? buck: on ? iweak : off ? isafe: off ? flag : low ? qfet: off dpp ? buck: on ? iweak : off ? isafe: off ? flag : high ? qfet: on ? v sensn < v rechg and - pwr_path = 1 ? v bat NCP1850 http://onsemi.com 20 i 2 c description NCP1850 can support a subset of i 2 c protocol, below are detailed introduction for i 2 c programming. start ic adress 1 1 read ack data 1 ack data n /ack stop start ack ic adress 0 0 write data 1 ack data n ack /ack stop from mcu to ncpxxxx from ncpxxxx to mcu read out from part write inside part figure 11. general protocol description if part down not acknowledge, the /nack will be followed b a stop or sr if part acknowledges, the ack can be followed by another data or stop or sr the first byte transmitted is the chip address (with lsb bit sets to 1 for a read operation, or sets to 0 for a write operation ). then the following data will be: ? in case of a write operation, the register address (@reg) we want to write in followed by the data we will write in the chip. the writing process is incremental. so the first data will be written in @reg, the second one in @reg + 1 . the data are optional. ? in case of read operation, the NCP1850 will output the data out from the last register that has been accessed by the last write operation. like writing process, reading process is an incremental process. read out from part the master will first make a ?pseudo w rite? transaction with no data to set the internal address register. then, a stop then st art or a repeated start will initiate the read transaction from the register address the initial write transaction has set: stop ic adress 1 1 read ack start ic adress 0 0 write register adress ack start ack data 1 data n ack /ack stop stets internal register pointer register adress value register adress + (n ? 1) value n registers read from mcu to ncpxxxx from ncpxxxx to mcu figure 12. read out from part the first write sequence will set the internal pointer on the register we want access to. then the read transaction will start at the address the write transaction has initiated. write in part: write operation will be achieved by only one transaction. after chip address, the mcu first data will be the internal register we want access to, then following data will be the data we want to write in reg, reg + 1, reg + 2, ., reg +n. NCP1850 http://onsemi.com 21 write n registers: reg + (n ? 1) value ack stop from mcu to ncpxxxx from ncpxxxx to mcu start ic adress 0 0 write ack register reg0 adress ack reg value ack sets internal register pointer write value in register reg0 write value in register reg + (n ? 1) n registers write figure 13. write in n registers i 2 c address ncp1851 has fixed i 2 c but different i 2 c address (0$10, 7 bit address, see below table a7~a1), ncp1851 supports 7 ? bit address only. table 5. NCP1850 i 2 c address i 2 c address (note 10) hex a7 a6 a5 a4 a3 a2 a1 a0 default $6c / $6d 0 1 1 0 1 1 0 x 10. other addresses are available upon request. table 6. registers map bit type reset name rst value function status register ? memory location: 00 7 ? 4 r no_reset state[3:0] 0000 charge mode: ? 0000: off ? 0001: wait + stby ? 0010: safe charge ? 0011: pre charge ? 0100: full charge ? 0101: voltage charge ? 0110: charge done ? 0111: dpp ? 1000: weak wait ? 1001: weak safe ? 1010: weak charge ? 1011: fault boost mode: ? 1100: boost wait(s_wait) ? 1101: boost mode (s_on) ? 1110: boost fault( s_fault) ? 1111: boost over load (s_ol)) 3 r no_reset batfet 0 indicate if a batfet is connected: 0: no batfet is connected 1: batfet is connected. 2 r no_reset ntc 0 indicate if a ntc resistor is present: 0: no ntc connected 1: ntc connected 1 r no_reset statint 0 status interrupt: 0: no status interrupt 1: interruption flagged on stat_int register 0 r no_reset faultint 0 fault interrupt: 0: no status interrupt 1: interruption flagged on chrin1, chrin2 or bst_int register ctrl1 register ? memory location: 01 7 rw off state, por, reg_rst reg_rst 0 reset: 0: no reset 1: reset all registers NCP1850 http://onsemi.com 22 table 6. registers map bit function rst value name reset type ctrl1 register ? memory location: 01 6 rw off state, por, reg_rst chg_en 1 charge control: 0: halt charging (go to fault state) or otg operation 1: charge enabled / charge resume 5 rw off state, por, reg_rst, chgmode otg_en 0 on the go enable: 0: no otg operation 1: otg operation (set by i2c or otg pin) 4 rw off state, por, reg_rst ntc_en 1 ntc pin operation enable: 0:battery temperature ignore, 1: battery temperature modify the charge profile. 3 rw off state, por, reg_rst tj_warn_opt 0 enable charge current vs junction temperature 0: no current change versus junction temperature 1: charge current is reduced when tj is too high. 2 rw off state, por, reg_rst chg_halt 0 force end of charge 0: normal end of charge condition 1: force eoc condition if vbat > vrechg 1 rw off state, por, reg_rst, trm_rst tchg_rst 0 charge timer reset: 0: no reset 1: reset and resume charge timer (tchg timer)(self clearing) 0 rw off state, por, reg_rst int_mask 1 intb global interrupt mask 0: all interrupts can be active. 1: all interrupts are not active ctrl2 register ? memory location: 02 7 rw off state, por, reg_rst, otgmode wdto_dis 0 disable watchdog timer 0: watchdog timer enable 1: watchdog timer disable 6 rw off state, por, reg_rst, otgmode chgto_dis 0 disable charge timer 0: charge timer enable 1: charge timer disable 5 rw off state, por, reg_rst, otgmode pwr_path 0 power path management: 0: power path disable 1: power path enable 4 rw off state, por, reg_rst trans_en_reg 1 trans pin operation enable: 0 : trans pin is still off 1 : trans pin is supply 3 rw off state, por, reg_rst int_flg_mask 1 flag global interrupt mask 0 : all interrupts are active. 1 : all interrupts are not active 2 rw off state, por, reg_rst, otgmode iinset_pin_en 1 enable input current set pin: 0: input current limit and aicl control by i 2 c 1: input current limit and aicl control by pins ilimx 1 rw off state, por, reg_rst, otgmode iinlim_en 1 enable input current limit: 0: no input current limit 1: input current limit is iinlim[3:0] 0 rw off state, por, reg_rst, otgmode aicl_en 0 enable automatic charge current: 0: no aicl 1: aicl stat_int register ? memory location: 03 7 ? 6 r no_reset reserved 5 rcdual off state, por, reg_rst twarn 0 0: silicon temperature is below twarn threshold 1: silicon temperature is above twarn threshold NCP1850 http://onsemi.com 23 table 6. registers map bit function rst value name reset type stat_int register ? memory location: 03 4 rcdual off state, por, reg_rst tm1 0 0: silicon temperature is below t1 threshold 1: silicon temperature is above t1 threshold 3 rcdual off state, por, reg_rst tm2 0 0: silicon temperature is below t2 threshold 1: silicon temperature is above t2 threshold 2 rcdual off state, por, reg_rst tsd 0 0: silicon temperature is below tsd threshold 1: silicon temperature is above tsd threshold 1 r no_reset reserved 0 0 rcdual off state, reg_rst, por, otgmode vbusok 0 0: changer not in usb range 1: charger in usb charging range vbusuv < vin < vbusov ch1_int register ? memory location: 04 7 ? 5 r no_reset reserved 0 4 rcdual off state, reg_rst, por, otgmode vinlo 0 vin changer detection interrupt: 1: vin ? vbat > vchgdet and vin < vindet 3 rcdual off state, reg_rst, por, otgmode vinhi 0 vin over voltage lock out interrupt: 1: vin > vinov 2 rcdual off state, reg_rst, por, otgmode batrmv 0 battery temp out of range interrupt: 1: vntc > vntcrmv 1 rcdual off state, reg_rst, por, otgmode buckovp 0 vbat over voltage interrupt: 1: vbat > vovp 0 r no_reset chint2 0 charger related interrupt (ch2_int register) ch2_int register ? memory location: 05 7 rcdual off state, reg_rst, por, otgmode ntchot 0 battery temperature exceeds ntc hot threshold 5 ? 6 r no_reset reserved 00 4 rcdual off state, reg_rst, por, otgmode ntccold 0 battery temperature is lower than ntc cold threshold 3 rcsingl e off state, por, reg_rst, trm_rst, otgmode wdto 0 watchdog timeout expires interrupt: 1: 32s timer expired. 2 rcsingl e off state, por, reg_rst, trm_rst, otgmode usbto 0 usb timeout expires initerrupt: 1: 2048s timer expired 1 rcsingl e off state, por, reg_rst, trm_rst, otgmode chgto 0 charge timeout expires interrupt: 1: 3600s timer expired 0 r no_reset chint1 0 charger related interrupt (ch1_int register) bst_int register ? memory location: 06 7 ? 3 r no_reset reserved 00000 2 rcdual off state, por, reg_rst, chgmode vbusilim 0 vbus overload interrupt: 1: vbus voltage < vbusuv NCP1850 http://onsemi.com 24 table 6. registers map bit function rst value name reset type bst_int register ? memory location: 06 1 rcdual off state, por, reg_rst, chgmode vbusov 0 vbus overvoltage interrupt: 1: vbus voltage < vbusov 0 rcdual off state, por, reg_rst, chgmode vbatlo 0 vbat overvoltage interrupt: 1: vbat voltage < vibstl vin_sns register ? memory location: 07 7 r no_reset vinovlo_sns 0 vin over voltage lock out comparator 1: vin > vinov 6 r no_reset reserved 0 5 r no_reset vbusov_sns 0 vin not is usb range comparator 1: vin > vbusov 4 r no_reset vbusuv_sns 0 vin not is usb range comparator 1: vin < vbusuv 3 r no_reset vindet_sns 0 vin voltage detection comparator 1: vin > vindet 2 r no_reset vchgdet_sns 0 vin changer detection comparator 1: vin ? vbat > vchgdet 1 r no_reset vboost_uv_sns 0 vin otg under voltage comparator 1: vin < vbusuv 0 r no_reset reserved 0 vbat_sns register ? memory location: 08 7 r no_reset ntc_removal_s ns 0 ntc removal comparator : 1: battery removal, vntc > vntcrmv 6 r no_reset vbat_ov_sns 0 vbat over voltage comparator 1: vbat > vovp 5 r no_reset vrechg_ok_sns 0 vbat recharge comparator 1: vbat > vrechg 4 r no_reset vfet_ok_sns 0 vbat weak charge comparator 1: vbat > vfet 3 r no_reset vpre_ok_sns 0 vbat precharge comparator 1: vbat > vpre 2 r no_reset vsafe_ok_sns 0 vbat safe comparator 1: vbat > vsafe 1 r no_reset ieoc_ok_sns 0 end of charge current comparator 1: icharge > ieoc 0 r no_reset reserved 0 temp_sns register ? memory location: 09 7 r no_reset ntc_cold_sns 0 ntc cold comparator : 1: vntc < vcold 5 ? 6 r no_reset reserved 00 4 r no_reset ntc_hot_sns 0 ntc disable comparator : 1: vntc > vntcdis 3 r no_reset tsd_sns 0 chip thermal shut down comparator 1: chip temp > tsd 2 r no_reset tm2_sns 0 chip thermal shut down comparator 1: chip temp > tm2 NCP1850 http://onsemi.com 25 table 6. registers map bit function rst value name reset type temp_sns register ? memory location: 09 1 r no_reset tm1_sns 0 chip thermal shut down comparator 1: chip temp > tm1 0 r no_reset twarn 0 chip thermal shut down comparator 1: chip temp > twarn stat_msk register ? memory location: 0a 7 ? 6 r no_reset reserved 00 5 rw off state, por, reg_rst twarn_mask 1 twarn interruption mask bit. 4 rw off state, por, reg_rst tm1_mask 1 tm1 interruption mask bit. 3 rw off state, por, reg_rst tm2_mask 1 tm2 interruption mask bit. 2 rw off state, por, reg_rst tsd_mask 1 tsd interruption mask bit. 1 r no_reset reserved 0 0 rw off state, por, reg_rst, otgmode vbusok_mask 1 vbusok interruption mask bit. ch1_msk register ? memory location: 0b 7 ? 5 r no_reset reserved 000 4 rw off state, por, reg_rst, otgmode vinlo_mask 1 vinlo interruption mask bit. 3 rw off state, por, reg_rst, otgmode vinhi_mask 1 vinhi interruption mask bit. 2 rw off state, por, reg_rst, otgmode batrmv_mask 1 batrmv interruption mask bit. 1 rw off state, por, reg_rst, otgmode buckovp_mask 1 buckovp interruption mask bit. 0 r no_reset reserved 0 ch2_msk register ? memory location: 0c 7 rw off state, por, reg_rst, otgmode ntchot_mask 1 ntchot interruption mask bit. 5 ? 6 r no_reset reserved 0 4 rw off state, por, reg_rst, otgmode ntccold_mask 1 ntccold interruption mask bit. 3 rw off state, por, reg_rst, otgmode wdto_mask 0 wdto interruption mask bit. 2 rw off state, por, reg_rst, otgmode usbto_mask 0 usbto interruption mask bit. 1 rw off state, por, reg_rst, otgmode chgto_mask 0 chgto interruption mask bit. NCP1850 http://onsemi.com 26 table 6. registers map bit function rst value name reset type ch2_msk register ? memory location: 0c 0 r no_reset reserved 0 bst_msk register ? memory location: 0d 7 ? 4 r no_reset reserved 0000 3 rw off state, por, reg_rst, otgmode vbusilim_mask 1 vbusilim interruption mask bit. 2 rw off state, por, reg_rst, otgmode vbusov_mask 1 vbusov interruption mask bit. 1 rw off state, por, reg_rst, otgmode vbatlo_mask 1 vbatlo interruption mask bit. 0 rw off state, por, reg_rst, otgmode stateotg_mask 1 stateotg interruption mask bit. vbat_set register ? memory location: 0e 7 ? 6 r no_reset reserved 00 0 ? 5 rw off state, por, reg_rst, otgmode ctrl_vbat [5:0] 001100 000000: 3.3 v 001100: 3.6 v 110000: 4.5 v step: 0.025 v ibat_set register ? memory location: 0f 7 r no_reset reserved 0 6 ? 4 rw off state, por, reg_rst, otgmode ieoc[2:0] 010 000: 100 ma 010: 150 ma 111: 275 ma step: 25 ma 3 ? 0 rw off state, por, reg_rst, otgmode ichg[3:0] 0110 output range current programmable range: 0000: 400 ma 1011: 1.5 a step : 100 ma misc_set register ? memory location: 10 7 rw off state, por, reg_rst, otgmode tst_set 0 minimum transition time from weak charge to full charge state 0 : 32 s 1 : 16 ms 6 rw off state, por, reg_rst, otgmode fctry_mod_reg 0 factory mode : 0: factory mode disable 1: enable factory mode. 5 rw off state, por, reg_rst, otgmode iweak_en 1 charge current during weak battery states: 0: disable 1: 100 ma 4 ? 2 rw off state, por, reg_rst, otgmode ctrl_vfet[2:0] 011 battery to system re ? connection threshold: 000: 3.1 v 001: 3.2 v 010: 3.3 v 011: 3.4 v 100: 3.5 v 101: 3.6 v 1 ? 0 rw off state, por, reg_rst, otgmode iinlim[1:0] 00 input current limit range: 00: 100 ma 01: 500 ma 10: 900 ma 11: 1500 ma NCP1850 http://onsemi.com 27 table 6. registers map bit function rst value name reset type ntc_set register ? memory location: 11 7 ? 4 r no_reset reserved 0000 2 ? 3 rw off state, por, reg_rst, otgmode batcold[1:0] 01 r0 = 10 k , t0= 25 c b = 3380 00: ? 1 c 01: 2 c 10: 5 c 11: 9 c b = 3400 00: 1 c 01: 5 c 10: 8 c 11: 11 c 0 ? 1 rw off state, por, reg_rst, otgmode bathot[1:0] 10 r0 = 10 k ,t0= 25 c b = 3380 |00: 43 c 01: 47 c 10: 52 c 11: 57 c b = 3400 00: 40 c 01: 44 c 10: 48 c 11: 52 c application information components selection inductor l1 ncp1851 is recommended to be used with 2.2 h inductor. below will give inductor ripple and maximum current for two different application cases knowing the following relation: i l v bat 1 v bat v in 1 l1 f swchg the worst case is when v bat v bat 2 v in is maximum i lmax v in 4 1 l1 f swchg ;i peakmax i chg i lmax 2 so when v bat v in 2 capacitor c6 a 10 f output capacitor is recommended for proper operation and design stability. the bandwidth of the system is defined by the following relation: f bw 1 2 l 1 c 6 33 khz the bandwidth is recommended to be high enough in case of application with a batfet because the system can be directly connected to the buck output. and in this case, the battery does not play any role upon a load transient as it?s disconnected from the buck converter. usb dedicated charge v in = 5 v v chg = 4.2 v i chg = 1.5 a l1 = 2.2 h il1 = 0.189 a i peakmax = 1.59 a ac adaptor charge v in = 16 v v chg = 4.2 v i chg = 1.5 a l1 = 2.2 h il1 = 0.6 a i peakmax = 1.8 a resistance r1 r 1 (charge current sense resistor) resistor is determined by considering thermal constrain as its value is 68 m typical. the power dissipation is given by: p r1 r 1 (i chg ) 2 the worst case is i chg = 1.5 a so p r1 = 0.153 w. NCP1850 http://onsemi.com 28 bill of material in flag scl sda spm cap ntc bat fet weak sensn sensp cboot sw ilim agnd pgnd otg + NCP1850 core system vbus d+ d ? gnd c in c cap c core c boot c out r sns l x 4.7 f 2.2 f 1 f 10nf 2.2 h 68m 10 f q bat (*) intb trans c trans 100nf figure 14. NCP1850 typical application example item part description ref value pcb footprint manufacturer manufacturer reference 1 ceramic capacitor 25 v x5r c in 1 f 0603 murata grm188r61e105k 2 ceramic capacitor 25 v x5r c cap 4.7 f 0805 murata grm21br61e475ka12l 3 ceramic capacitor 6.3 v x5r c core 2.2 f 0402 murata grm155r60j225m 4 ceramic capacitor 6.3 v x5r c trs 0.1 f 0402 murata grm155r60j104k 5 ceramic capacitor 10 v x5r c boot 10 nf 0402 murata grm155r60j103k 6 ceramic capacitor 6.3 v x5r c out 10 f 0603 murata grm188r60j106m 7 smd inductor l x 2.2 h 3012 tdk vls3012t ? 2r2m1r5 8 smd resistor 0.25 w, 1% r sns 68 m 0603 panasonic erj3bwfr068v 9 power channel p ? mosfet q bat 30 m udfn 2 * 2 mm on semiconductor ntlus3a40pz pcb layout consideration particular attention must be paid with c core capacitor as it?s decoupling the supply of internal circuitry including gate driver. this capacitor must be placed between core pin and pgnd pin with a minimum track length. the high speed operation of the NCP1850 demands careful attention to board layout and component placement. to prevent electromagnetic interference (emi) problems, attention should be paid specially with components c in , l x , c cap , and c out as they constitute a high frequency current loop area. the power input capacitor c in , connected from in to pgnd, should be placed as close as possible to the NCP1850. the output inductor l x and the output capacitor c out connected between r sns and pgnd should be placed close to the ic. c cap capacitor should also be place as close as possible to cap and pgnd pin. the high current charge path through in, cap, sw, inductor l1, resistor r1, optional baftet, and battery pack must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. an iweak current can flow through weak and bat traces witch defines the appropriate track width. it?s suggested to keep as complete ground plane under NCP1850 as possible. pgnd and agnd pin connection must be connected to the ground plane. care should be taken to avoid noise interference between pgnd and agnd. finally it is always good practice to keep the sensitive tracks such as feedbacks connections (sensp, sensn, bat) away from switching signal connections by laying the tracks on the other side or inner layer of pcb. NCP1850 http://onsemi.com 29 r sns l x 2.2 f sw in cap pgnd q1 q2 q3 core c sys 10 f + c in 1 f c cap 4.7 f c core 2.2 f power path NCP1850 noise sensitive path figure 15. NCP1850 power path 68m 68m ordering information part number i 2 c address package shipping ? NCP1850fcct1g $6c wlcsp25 (pb ? free) tbd ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. NCP1850 http://onsemi.com 30 package dimensions wlcsp25, 2.06x2.06 case 567fz issue o seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 2.06 bsc e b 0.24 0.29 e 0.40 bsc 0.60 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 25x b 45 c b a 0.10 c a a1 a2 c 0.17 0.23 2.06 bsc 0.25 25x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.10 c 2x top view side view bottom view note 3 e a2 0.36 ref recommended package outline 123 pitch d e pitch a1 a2 detail a die coat a3 detail a a3 0.04 ref on semiconductor and are registered trademar ks of semiconductor components industries, llc (s cillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to an y products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of th e application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products ar e not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associ ated with such unintended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action em ployer. this literature is subject to all applicable copyrig ht laws and is not fo r resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCP1850/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative |
Price & Availability of NCP1850
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |